Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors

[ES] Los procesadores multinúcleo actuales cuentan con recursos compartidos entre los diferentes núcleos. Dos de estos recursos compartidos, la cache de último nivel y el ancho de banda de memoria principal, pueden convertirse en cuellos de botella para el rendimiento. Además, con el crecimiento del número de núcleos que implementan los diseños más recientes, la red dentro del chip también se convierte en un cuello de botella que puede afectar negativamente al rendimiento, ya que las redes tradicionales pueden encontrar limitaciones a su escalabilidad en el futuro cercano. Prácticamente la totalidad de los diseños actuales implementan jerarquías de memoria que se comunican mediante rápidas redes de interconexión. Esta organización es eficaz dado que permite reducir el número de accesos que se realizan a memoria principal y la latencia media de acceso a memoria. Las caches, la red de interconexión y la memoria principal, conjuntamente con otras técnicas conocidas como la prebúsqueda, permiten reducir las enormes latencias de acceso a memoria principal, limitando así el impacto negativo ocasionado por la diferencia de rendimiento existente entre los núcleos de cómputo y la memoria. Sin embargo, compartir los recursos mencionados es fuente de diferentes problemas y retos, siendo uno de los principales el manejo de la interferencia entre aplicaciones. Hacer un uso eficiente de la jerarquía de memoria y las caches, así como contar con una red de interconexión apropiada, es necesario para sostener el crecimiento del rendimiento en los diseños tanto actuales como futuros. Esta tesis analiza y estudia los principales problemas e inconvenientes observados en estos dos recursos: la cache de último nivel y la red dentro del chip. En primer lugar, se estudia la escalabilidad de las tradicionales redes dentro del chip con topología de malla, así como esta puede verse comprometida en próximos diseños que cuenten con mayor número de núcleos. Los resultados de este estudio muestran que, a mayor número de núcleos, el impacto negativo de la distancia entre núcleos en la latencia puede afectar seriamente al rendimiento del procesador. Como solución a este problema, en esta tesis proponemos una de red de interconexión óptica modelada en un entorno de simulación detallado, que supone una solución viable a los problemas de escalabilidad observados en los diseños tradicionales. A continuación, esta tesis dedica un esfuerzo importante a identificar y proponer soluciones a los principales problemas de diseño de las jerarquías de memoria actuales como son, por ejemplo, el sobredimensionado del espacio de cache privado, la existencia de réplicas de datos y rigidez e incapacidad de adaptación de las estructuras de cache. Aunque bien conocidos, estos problemas y sus efectos adversos en el rendimiento pueden ser evitados en procesadores de alto rendimiento gracias a la enorme capacidad de la cache de último nivel que este tipo de procesadores típicamente implementan. Sin embargo, en procesadores de bajo consumo, no existe la posibilidad de contar con tales capacidades y hacer un uso eficiente del espacio disponible es crítico para mantener el rendimiento. Como solución a estos problemas en procesadores de bajo consumo, proponemos una novedosa organización de jerarquía de dos niveles cache que utiliza una red de interconexión óptica. Los resultados obtenidos muestran que, comparado con diseños convencionales, el consumo de energía estática en la arquitectura propuesta es un 60% menor, pese a que los resultados de rendimiento presentan valores similares. Por último, hemos extendido la arquitectura propuesta para dar soporte tanto a aplicaciones paralelas como secuenciales. Los resultados obtenidos con la esta nueva arquitectura muestran un ahorro de hasta el 78 % de energía estática en la ejecución de aplicaciones paralelas.[CA] Els processadors multinucli actuals compten amb recursos compartits entre els diferents nuclis. Dos d'aquests recursos compartits, la memòria d’últim nivell i l'ample de banda de memòria principal, poden convertir-se en colls d'ampolla per al rendiment. A mes, amb el creixement del nombre de nuclis que implementen els dissenys mes recents, la xarxa dins del xip també es converteix en un coll d'ampolla que pot afectar negativament el rendiment, ja que les xarxes tradicionals poden trobar limitacions a la seva escalabilitat en el futur proper. Pràcticament la totalitat dels dissenys actuals implementen jerarquies de memòria que es comuniquen mitjançant rapides xarxes d’interconnexió. Aquesta organització es eficaç ates que permet reduir el nombre d'accessos que es realitzen a memòria principal i la latència mitjana d’accés a memòria. Les caches, la xarxa d’interconnexió i la memòria principal, conjuntament amb altres tècniques conegudes com la prebúsqueda, permeten reduir les enormes latències d’accés a memòria principal, limitant així l'impacte negatiu ocasionat per la diferencia de rendiment existent entre els nuclis de còmput i la memòria. No obstant això, compartir els recursos esmentats és font de diversos problemes i reptes, sent un dels principals la gestió de la interferència entre aplicacions. Fer un us eficient de la jerarquia de memòria i les caches, així com comptar amb una xarxa d’interconnexió apropiada, es necessari per sostenir el creixement del rendiment en els dissenys tant actuals com futurs. Aquesta tesi analitza i estudia els principals problemes i inconvenients observats en aquests dos recursos: la memòria cache d’últim nivell i la xarxa dins del xip. En primer lloc, s'estudia l'escalabilitat de les xarxes tradicionals dins del xip amb topologia de malla, així com aquesta es pot veure compromesa en propers dissenys que compten amb major nombre de nuclis. Els resultats d'aquest estudi mostren que, a major nombre de nuclis, l'impacte negatiu de la distància entre nuclis en la latència pot afectar seriosament al rendiment del processador. Com a solució' a aquest problema, en aquesta tesi proposem una xarxa d’interconnexió' òptica modelada en un entorn de simulació detallat, que suposa una solució viable als problemes d'escalabilitat observats en els dissenys tradicionals. A continuació, aquesta tesi dedica un esforç important a identificar i proposar solucions als principals problemes de disseny de les jerarquies de memòria actuals com son, per exemple, el sobredimensionat de l'espai de memòria cache privat, l’existència de repliques de dades i la rigidesa i incapacitat d’adaptació' de les estructures de memòria cache. Encara que ben coneguts, aquests problemes i els seus efectes adversos en el rendiment poden ser evitats en processadors d'alt rendiment gracies a l'enorme capacitat de la memòria cache d’últim nivell que aquest tipus de processadors típicament implementen. No obstant això, en processadors de baix consum, no hi ha la possibilitat de comptar amb aquestes capacitats, i fer un us eficient de l'espai disponible es torna crític per mantenir el rendiment. Com a solució a aquests problemes en processadors de baix consum, proposem una nova organització de jerarquia de dos nivells de memòria cache que utilitza una xarxa d’interconnexió òptica. Els resultats obtinguts mostren que, comparat amb dissenys convencionals, el consum d'energia estàtica en l'arquitectura proposada és un 60% menor, malgrat que els resultats de rendiment presenten valors similars. Per últim, hem estes l'arquitectura proposada per donar suport tant a aplicacions paral·leles com seqüencials. Els resultats obtinguts amb aquesta nova arquitectura mostren un estalvi de fins al 78 % d'energia estàtica en l’execució d'aplicacions paral·leles.[EN] Current multicores face the challenge of sharing resources among the different processor cores. Two main shared resources act as major performance bottlenecks in current designs: the off-chip main memory bandwidth and the last level cache. Additionally, as the core count grows, the network on-chip is also becoming a potential performance bottleneck, since traditional designs may find scalability issues in the near future. Memory hierarchies communicated through fast interconnects are implemented in almost every current design as they reduce the number of off-chip accesses and the overall latency, respectively. Main memory, caches, and interconnection resources, together with other widely-used techniques like prefetching, help alleviate the huge memory access latencies and limit the impact of the core-memory speed gap. However, sharing these resources brings several concerns, being one of the most challenging the management of the inter-application interference. Since almost every running application needs to access to main memory, all of them are exposed to interference from other co-runners in their way to the memory controller. For this reason, making an efficient use of the available cache space, together with achieving fast and scalable interconnects, is critical to sustain the performance in current and future designs. This dissertation analyzes and addresses the most important shortcomings of two major shared resources: the Last Level Cache (LLC) and the Network on Chip (NoC). First, we study the scalability of both electrical and optical NoCs for future multicoresand many-cores. To perform this study, we model optical interconnects in a cycle-accurate multicore simulation framework. A proper model is required; otherwise, important performance deviations may be observed otherwise in the evaluation results. The study reveals that, as the core count grows, the effect of distance on the end-to-end latency can negatively impact on the processor performance. In contrast, the study also shows that silicon nanophotonics are a viable solution to solve the mentioned latency problems. This dissertation is also motivated by important design concerns related to current memory hierarchies, like the oversizing of private cache space, data replication overheads, and lack of flexibility regarding sharing of cache structures. These issues, which can be overcome in high performance processors by virtue of huge LLCs, can compromise performance in low power processors. To address these issues we propose a more efficient cache hierarchy organization that leverages optical interconnects. The proposed architecture is conceived as an optically interconnected two-level cache hierarchy composed of multiple cache modules that can be dynamically turned on and off independently. Experimental results show that, compared to conventional designs, static energy consumption is improved by up to 60% while achieving similar performance results. Finally, we extend the proposal to support both sequential and parallel applications. This extension is required since the proposal adapts to the dynamic cache space needs of the running applications, and multithreaded applications's behaviors widely differ from those of single threaded programs. In addition, coherence management is also addressed, which is challenging since each cache module can be assigned to any core at a given time in the proposed approach. For parallel applications, the evaluation shows that the proposal achieves up to 78% static energy savings. In summary, this thesis tackles major challenges originated by the sharing of on-chip caches and communication resources in current multicores, and proposes new cache hierarchy organizations leveraging optical interconnects to address them. The proposed organizations reduce both static and dynamic energy consumption compared to conventional approaches while achieving similar performance; which results in better energy efficiency.Puche Lara, J. (2021). Novel Cache Hierarchies with Photonic Interconnects for Chip Multiprocessors [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/165254TESI

Estudio de la viabilidad de una red híbrida foto-eléctrica

[ES] Recientemente, las redes ópticas han aparecido como una alternativa a las redes eléctricas dentro del chip, por su bajo consumo, alto ancho de banda, y latencia independiente de la distancia. Sin embargo, el coste temporal requerido por la conversión electro-óptica y viceversa de la información así como el coste de la integración de estas tecnologías en los procesos de fabricación actuales hace pensar que la implantación de las redes ópticas on-chip será gradual. Por tanto, es de esperar que en los próximos años convivirán ambas tecnologías. En este proyecto se analiza la viabilidad de algunas propuestas de redes híbridas que combinan ambas tecnologías.Puche Lara, J. (2015). Estudio de la viabilidad de una red híbrida foto-eléctrica. http://hdl.handle.net/10251/55233TFG

FOS: a low-power cache organization for multicores

[EN] The cache hierarchy of current multicore processors typically consists of one or two levels of private caches per core and a large shared last-level cache. This approach incurs area and energy wasting due to oversizing the private cache space, data replication through the inclusive cache levels, as well as the use of highly set-associative caches. In this paper, we claim that although this is the commonly adopted approach, it presents important design issues that can be addressed by a more energy efficient organization. This work proposes Flat On-chip Storage (FOS), a novel cache organization that, aimed at addressing energy and area on low-power processors, resolves the mentioned issues. For this purpose, FOS combines L2 and L3 cache levels into a single one, organized as a flat space, and composed of a pool of private small cache slices. These slices are initially powered off to save energy, and they are powered on and assigned to cores provided that the system performance is expected to improve. To provide fast and uniform access from the private L1 caches to the FOS's cache slices, multiple architectural challenges are overcome, which entails the design of a custom optical network-on-chip. Experimental results show that FOS achieves significant energy savings on both static and dynamic energy over conventional cache organizations with the same storage capacity. FOS static energy savings are as much as 60% over an electrically connected shared cache; these savings grow up to 75% compared to optically connected baselines. Moreover, despite deactivating part of the cache space, FOS achieves similar performance values as those achieved by conventional approaches.Puche-Lara, J.; Petit Martí, SV.; Sahuquillo Borrás, J.; Gómez Requena, ME. (2019). FOS: a low-power cache organization for multicores. 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In: Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA’09, pp 441–450. https://doi.org/10.1145/1555754.1555809Demir Y, Hardavellas N (2015) Parka: thermally insulated nanophotonic interconnects. In: NOCS ’15, pp 1:1–1:8. https://doi.org/10.1145/2786572.2786597Duan GH, Fedeli JM, Keyvaninia S, Thomson D (2012) 10 gb/s integrated tunable hybrid iii-v/si laser and silicon mach-zehnder modulator. In: European Conference and Exhibition on Optical Communication. https://doi.org/10.1364/ECEOC.2012.Tu.4.E.2Dybdahl H, Stenstrom P (2007) An adaptive shared/private NUCA cache partitioning scheme for chip multiprocessors. In: 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp 2–12. https://doi.org/10.1109/HPCA.2007.346180García A, Fernández R, Garca JM, Bartolini S (2014) Managing resources dynamically in hybrid photonic-electronic networks-on-chip. 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Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework

© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Photonic interconnects are a promising solution for the so-called communication bottleneck in current Chip Multiprocessor (CMPs) architectures. This technology presents an inherent low-latency and power consumption almost independent of communication distance, which are really desirable features in future Networks on Chip for next CMPs generations. However, since nanophotonic technology is still growing and therefore in an immature state, current simulators of detailed systems may not provide accurate models of photonic components. In this context, non-representative results are obtained when unaccurate photonic models are assumed. This paper summarizes all of the components that conform a fully operative photonic NoC and presents their current state of the art. Moreover, we evaluate a realistic photonic network that consists of two photonic rings and a token-based arbitration mechanism and compare it against a non-realistic model. In addition, both realistic and non-realistic schemes are valuated under different configurations varying the number of wavelengths that photonic waveguides employ. The experimental results show that the non-realistic NoC presents up 6× network latency deviation with respect to the accurate model. This deviation is translated into a performance deviation higher than 10% in several applications studied, which demonstrates the importance of accurate models when simulating current technologies under development like nanophotonics. Finally, a power consumption model of the realistic photonic network is presented. The results show that the overall photonic network power consumption grows with the number of wavelengths per waveguide since the number of required modulators and receivers becomes higher. In this way, the proposed realistic photonic network, which employs only two wavelengths for arbitration and destination selection tasks, increases its power consumption up to 3%, so network designs with more complex arbitration mechanisms must take into account the impact of the number of wavelengths on the power consumption.This work was supported by the Spanish Ministerio de Economía y Competitividad (MINECO) and by Plan E funds under Grant TIN2015-66972-C5-1-R and the ExaNest project, funded by the European Union’s Horizon 2020 research andinnovation programme under grant agreement No 671553.Puche Lara, J.; Lechago Buendía, S.; Petit Martí, SV.; Gómez Requena, ME.; Sahuquillo Borrás, J. (2016). Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework. IEEE. https://doi.org/10.1109/HPCSim.2016.756836

Cooperative and Escaping Mechanisms between Circulating Tumor Cells and Blood Constituents

Metastasis is the leading cause of cancer-related deaths and despite measurable progress in the field, underlying mechanisms are still not fully understood. Circulating tumor cells (CTCs) disseminate within the bloodstream, where most of them die due to the attack of the immune system. On the other hand, recent evidence shows active interactions between CTCs and platelets, myeloid cells, macrophages, neutrophils, and other hematopoietic cells that secrete immunosuppressive cytokines, which aid CTCs to evade the immune system and enable metastasis. Platelets, for instance, regulate inflammation, recruit neutrophils, and cause fibrin clots, which may protect CTCs from the attack of Natural Killer cells or macrophages and facilitate extravasation. Recently, a correlation between the commensal microbiota and the inflammatory/immune tone of the organism has been stablished. Thus, the microbiota may affect the development of cancer-promoting conditions. Furthermore, CTCs may suffer phenotypic changes, as those caused by the epithelial–mesenchymal transition, that also contribute to the immune escape and resistance to immunotherapy. In this review,we discuss the findings regarding the collaborative biological events among CTCs, immune cells, and microbiome associated to immune escape and metastatic progression

Infraestructura para la Comunicación Citizen - Smart City

La constante evolución del mundo urbano está generando continuamente nuevas necesidades y requisitos por parte de los ciudadanos. El aumento de las expectativas y exigencias de los mismos así como la mejora en la gestión de muchos de los aspectos de la ciudad han supuesto el comienzo del desarrollo de las Smart Cities. Las posibilidades en el marco de las mismas son múltiples, centrándose este proyecto en las más cercanas a los habitantes de la ciudad. Desde un punto de vista práctico, una Smart City resulta útil al ciudadano cuando es capaz de ofrecer servicios de interés al mismo. Éste ve la ciudad como una plataforma de soporte a la que pedir ayuda o información en caso de necesitarla. Teniendo esto en cuenta, la Ciudad Inteligente deberá contar con una robusta infraestructura sobre la que desplegar todo tipo de servicios en los que sus habitantes tengan potencial interés. En el presente proyecto se ha desarrollado una infraestructura de este tipo, así como un prototipo cliente en forma de aplicación móvil que permite acceder a la misma. En este Trabajo Fin de Grado se consigue una infraestructura escalable en servicios y fácilmente ampliable a las nuevas necesidades de los ciudadanos. Utilizando estos principios como eje en el diseño de la misma, se ha desarrollado una plataforma en la que es posible desplegar un total de siete servicios urbanos propuestos y establecer una comunicación ejemplo con uno de ellos. Esta comunicación supone la interacción final entre la ciudad y sus habitantes, ya que representa cómo los ciudadanos, a través de sus dispositivos móviles, pueden acceder de forma remota mediante una pequeña aplicación a todas las posibilidades que su ciudad les ofrece

Association of circulating tumour cells with early relapse and 18F-fluorodeoxyglucose positron emission tomography uptake in resected non-small-cell lung cancers.

More than 20% of lung cancer patients develop a recurrence, even after curative resection. We hypothesized that relapse may arise from the dissemination of circulating tumour cells (CTCs). This study evaluates the significance of CTC detection as regards the recurrence of non-small-cell lung cancer (NSCLC) in surgically resected patients. Secondly, we investigated the association between CTCs and the uptake of 18 F-fluorodeoxyglucose (FDG) by the primary tumour on a positron emission tomographic (PET) scan. In this single-centre prospective study, blood samples for analysis of CTCs were obtained from 102 patients with Stage I-IIIA NSCLC both before (CTC1) and 1 month after (CTC2) radical resection. CTCs were isolated using immunomagnetic techniques. The presence of CTCs was correlated with the maximum standardized uptake value (SUVmax) measured on preoperative FDG PET/computed tomographic scans. Recurrence free survival (RFS) analysis was performed. CTCs were detected in 39.2% of patients before and in 27.5% 1 month after the operation. The presence of CTCs after the operation was significantly correlated with SUVmax on PET scans, pathological stage and surgical approach. Only SUVmax was an independent predictor for the presence of CTC2 on multivariate analysis. Postoperative CTCs were significantly correlated with a shorter RFS ( P  = 0.005). In multivariate analysis, the presence of CTC2 was associated with RFS, independent of disease staging. Detection of CTCs 1 month after radical resection might be a useful marker to predict early recurrence in Stage I-III NSCLC. The SUVmax value of the primary tumour on preoperative PET scans was associated with the presence of CTC 1 month after the operation

Aportaciones al conocimiento de la flora briológica española. Nótula XVI: Musgos y hepáticas del Alto Tajo (Cuenca, Guadalajara, Teruel)

La brioflora del territorio estudiado incluye 158 taxones, 142 musgos y 16 hepáticas, de los cuales 21 son novedades regionales para Guadalajara, 21 para Cuenca y 3 para Teruel

MIC of amoxicillin/clavulanate according to CLSI and EUCAST: Discrepancies and clinical impact in patients with bloodstream infections due to Enterobacteriaceae

Objectives: To compare results of amoxicillin/clavulanate susceptibility testing using CLSI and EUCAST methodologies and to evaluate their impact on outcome in patients with bacteraemia caused by Enterobacteriaceae. Patients and methods: A prospective observational cohort study was conducted in 13 Spanish hospitals. Patients with bacteraemia due to Enterobacteriaceae who received empirical intravenous amoxicillin/clavulanate treatment for at least 48h were included. MICs were determined following CLSI and EUCAST recommendations. Outcome variables were: failure at the end of treatment with amoxicillin/clavulanate (FEAMC); failure at day 21; and 30 day mortality. Classification and regression tree (CART) analysis and logistic regression were performed. Results: Overall, 264 episodes were included; the urinary tract was the most common source (64.7%) and Escherichia coli themost frequent pathogen (76.5%). Fifty-two isolates (19.7%) showed resistance according to CLSI and 141 (53.4%) according to EUCAST. The kappa index for the concordance between the results of both committees was only 0.24. EUCAST-derived, but not CLSI-derived, MICs were associated with failure when considered as continuous variables. CART analysis suggested a 'resistance' breakpoint of > 8/4mg/L for CLSI-derived MICs; it predicted FEAMC in adjusted analysis (OR=1.96; 95% CI: 0.98-3.90). Isolates with EUCAST-derived MICs > 16/2 mg/L independently predicted FEAMC (OR=2.10; 95%CI: 1.05-4.21) and failure at day 21 (OR=3.01; 95%CI: 0.93-9.67).MICs.32/2mg/Lwere only predictive of failure among patientswith bacteraemia from urinary or biliary tract sources. Conclusions: CLSI and EUCAST methodologies showed low agreement for determining the MIC of amoxicillin/clavulanate. EUCAST-derived MICs seemed more predictive of failure than CLSI-derived ones. EUCAST-derived MICs > 16/2 mg/L were independently associated with therapeutic failure